1. Field of the Invention
The present invention relates to a semiconductor memory device that writes/reads data to/from a memory cell.
2. Description of Related Art
FIG. 1 illustrates a configuration of a DRAM (Dynamic Random Access Memory) as a conventional semiconductor memory device. The semiconductor memory device is provided with: a memory cell array in which memory cells 20 are arranged in a matrix form; a plurality of word lines WL that are arranged in a row direction of the memory cell array; a plurality of bit line pairs BL and BL (“  ” means logical negation, and is called a “bar”) that are provided in a column direction of the memory cell array; a plurality of sense amplifiers 103; a plurality of transistors 104a and 104b, local buses 105-1 and 105-2; a data amplifier 106; a bus 7; and a data input/output circuit 8.
The plurality of sense amplifiers 103 are respectively provided associated with the plurality of bit line pairs BL and BL. The plurality of transistors 104-a and 104-b are respectively provided between the plurality of bit line pairs BL and BL and the local buses 105-1 and 105-2. The plurality of transistors 104-a and 104-b each is an N-type MOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor).
The local buses 105-1 and 105-2 are, before a read operation and a write operation, precharged to a potential VDD that is a power source potential.
The memory cell 20 has an N-type MOSFET 21 and a capacitive element 22. A gate of the N-type MOSFET 21 is connected to the word line WL, and a drain thereof is connected to the bit line BL or BL. A source of the N-type MOSFET 21 is connected to one terminal of the capacitive element 22. The other terminal of the capacitive element 22 is grounded.
The sense amplifier 103 is provided with: P-type MOSFETs 31 and 33 and N-type MOSFETs 32 and 34 for constituting a flip-flop; and an N-type MOSFET 35. A source of the P-type MOSFET 31 is supplied with a potential SAP that is between the potential VDD and a ground potential GND, and a drain thereof is connected to the bit line BL. A source of the N-type MOSFET 32 is supplied with a potential SAN that is between the potential SAP and the ground potential GND, a drain thereof is connected to the drain of the P-type MOSFET 31, and a gate thereof is connected to a gate of the P-type MOSFET 31. A source of the P-type MOSFET 33 is supplied with the potential SAP, a drain thereof is connected to the gates of the P-type MOSFET 31 and the N-type MOSFET 32 and the bit line BL, and a gate thereof is connected to the drains of the P-type MOSFET 31 and the N-type MOSFET 32. A source of the N-type MOSFET 34 is supplied with the potential SAN, a drain thereof is connected to the drain of the P-type MOSFET 33, and a gate thereof is connected to the gate of the P-type MOSFET 33. A source of the N-type MOSFET 35 is grounded. A drain of the N-type MOSFET 35 is supplied with the potential SAN, and a gate thereof is supplied with an enable signal SAE.
FIG. 2 is a timing chart showing the read operation.
First, a decoded row address specifies one word line WL (selected word line WL) out of the plurality of word lines WL. In this case, the selected word line WL is supplied with a word line selection signal. At this time, a level of the word line selection signal is the high level “H”.
At the same time, a decoded row address specifies one bit line pair BL and BL (selected bit line pair BL and BL) out of the plurality of bit line pairs BL and BL. In this case, the sense amplifier 103 that is provided associated with the selected bit line pair BL and BL among the plurality of sense amplifiers 103 is supplied with the enable signal SAE. At this time, a level of the enable signal SAE is the high level “H”.
Also, gates of selected transistor 104-a and 104-b that are provided associated with the selected bit line pair BL and BL among the plurality of transistors 104-a and 104-b are supplied with a selection signal YSW. At this time, a level of the selection signal YSW is the high level “H”.
The N-type MOSFET 35 of the selected sense amplifier 103 is turned ON in response to the enable signal SAE “H”. The selected transistors 104-a and 104-b are turned ON in response to the selection signal YSW “H”, and thus the selected bit line pair BL and BL and the local buses 105-1 and 105-2 are electrically connected with each other. At this time, a data is read out from a selected memory cell 20 that is connected to the selected word line WL and one bit line of the selected bit line pair BL and BL, and a potential difference is generated between the selected bit line pair BL and BL. The selected sense amplifier 103 supplies the potential difference to the local buses 105-1 and 105-2 through the selected transistors 104-a and 104-b. The data amplifier 106 supplies the potential difference supplied to the local buses 105-1 and 105-2 to the bus 7. The data input/output circuit 8 outputs, as a read data, the potential difference supplied to the bus 7.
Next, the level of the enable signal SAE is switched from the high level “H” to the low level “L”. Also, the level of the word line selection signal is switched from the high level “H” to the low level “L”. At this time, the local buses 105-1 and 105-2 are precharged to the potential VDD.
FIG. 3 is a timing chart showing the write operation.
First, a decoded row address specifies one word line WL (selected word line WL) out of the plurality of word lines WL. In this case, the selected word line WL is supplied with a word line selection signal. At this time, the level of the word line selection signal is the high level “H”.
At the same time, a decoded row address specifies one bit line pair BL and BL (selected bit line pair BL and BL) out of the plurality of bit line pairs BL and BL. In this case, gates of the selected transistors 104-a and 104-b that are respectively provided associated with the selected bit line pair BL and BL among the plurality of transistors 104-a and 104-b are supplied with the selection signal YSW. The level of the selection signal is the high level “H”.
The selected transistors 104-a and 104-b are turned ON in response to the selection signal YSW “H”, and thus the selected bit line pair BL and BL and the local buses 105-1 and 105-2 are electrically connected with each other.
The data input/output circuit 8 supplies a write data to the bus 7. The data amplifier 106 supplies the write data supplied to the bus 7 to the selected bit line pair BL and BL through the local buses 105-1 and 105-2 and the selected transistors 104-a and 104-b. At this time, the write data is written to a selected memory cell 20 connected to the selected word line WL and one bit line (e.g., the bit line BL) of the selected bit line pair BL and BL.
Next, the level of the word line selection signal is switched from the high level “H” to the low level “L”. At this time, the local buses 105-1 and 105-2 are precharged to the potential VDD.
In order to write the data to the memory cell 20 in the write operation, the data amplifier 106 needs to drive not only the local buses 105-1 and 105-2 but also the selected bit line pair BL and BL through the selected transistors 104-a and 104-b to invert the data latched by the selected sense amplifier 103. It is therefore necessary to ensure a sufficiently long period of time for which the local buses 105-1 and 105-2 and the selected bit line pair BL and BL are electrically connected with each other. In other words, it is required to ensure a sufficiently long period of time for which the selection signal YSW “H” is supplied to the selected transistors 104-a and 104-b. 
Whereas, in the read operation, a period of time during which the local buses 105-1 and 105-2 and the bit line pair BL and BL are electrically connected with each other may be the same as that in the write operation.
In the read operation, assuming that a potential difference necessary for determining data of the selected memory cell 20 is denoted by ΔVo, the potential difference between the local buses 105-1 and 105-2 is just required to become ΔVo. Therefore, the period of time during which the local buses 105-1 and 105-2 and the selected bit line pair BL and BL are electrically connected with each other may need not be as long as that in the write operation. For example, according to a technique described in Japanese Patent Publication JP-H11-306758, a period of time during which a data line pair and a bit line pair are connected with each other in the read operation is made shorter than that in the write operation, and speeding-up is achieved.